Typical applications cover offline power supplies with a secondary power capability of 50W in wide range condition and W in single range or with doubler configuration. Burst mode operation is an additional feature of this device, offering the ability to operate in stand-by mode without extra components. Table 3. It provides internal bias current during start-up via an integrated high voltage current source which is switched off during normal operation.
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Typical applications cover off line power supplies with a secondary power capability of 50W in wide range condition and W in single range or with doubler configuration. Burst mode operation is an additional feature of this device, offering the possibility to operate in stand-by mode without extra components. It provides internal bias current during start-up via an integrated high voltage current source which is switched off during normal operation. The device is able to handle an unclamped current during its normal operation, assuring self protection against voltage surges, PCB stray inductance, and allowing a snubberless operation for low output power.
Primary side circuit common ground connection. Note that any overvoltage due to regulation loop failure is still detected by the error amplifier through the VDD voltage, which cannot overpass 13V. The output voltage will be somewhat higher than the nominal one, but still under control. After that, the current source is shut down, and the device tries to start up by switching again.
This pin is also connected to the error amplifier, in order to allow primary as well as secondary regulation configurations. In case of primary regulation, an internal 13V trimmed reference voltage is used to maintain VDD at 13V.
For secondary regulation, a voltage between 8. The COMP pin behaves as a constant current It is the output of the error transconductance amplifier, and allows for the connection of a compensation network to provide the desired transfer function of the regulation loop.
Its bandwidth can be easily adjusted to the needed value with usual components value. As stated above, secondary regulation configurations are also implemented through the COMP pin. When the COMP voltage is going below 0. This feature can be used to switch off the converter, and is automatically activated by the regulation loop whatever is the configuration to provide a burst mode operation in case of negligible output power or open load condition.
It provides also a synchronisation capability, when connected to an external frequency source. Unit V? Thus, the outer voltage control loop defines the level at which the inner loop regulates peak current through the power switch and the primary winding of the transformer.
Excellent open loop D. This results in an improved line regulation, instantaneous correction to line changes and better stability for the voltage regulation loop. Current mode topology also ensures good limitation in the case of short circuit. During a first phase the output current increases slowly following the dynamic of the regulation loop. Then it reaches the maximum limitation current internally set and finally stops because the power supply on VDD is no longer correct.
For specific applications the maximum peak current internally set can be overridden by externally limiting the voltage excursion on the COMP pin. This function prevents anomalous or premature termination of the switching pulse in the case of current spikes caused by primary side capacitance or secondary side rectifier reverse recovery time. FSW is the normal switching frequency. ISTBY is the minimum controllable current, corresponding to the minimum on time that the device is able to provide in normal operation.
Note that PSTBY may be affected by the efficiency of the converter at low load, and must include the power drawn on the primary auxiliary voltage. This situation leads to the shutdown mode where the power switch is maintained in the off state, resulting in missing cycles and zero duty cycle.
The above cycle repeats indefinitely, providing a burst mode of which the effective duty cycle is much lower than the minimum one when in normal operation. The equivalent switching frequency is also lower than the normal one, leading to a reduced consumption on the input mains lines. The output voltage remains regulated around the normal level, with a low frequency ripple corresponding to the burst mode.
The amplitude of this ripple is low, because of the output capacitors and of the low output current drawn in such conditions. As soon as the voltage on this pin reaches the high voltage threshold VDDon of the UVLO logic, the device turns into active mode and starts switching.
The start up current generator is switched off, and the converter should normally provide the needed current on the VDD pin through the auxiliary winding of the transformer, as shown on figure In case of abnormal condition where the auxiliary winding is unable to provide the low voltage supply current to the VDD pin i.
This low value of start-up duty cycle prevents the stress of the output rectifiers and of the transformer when in short circuit. The external capacitor CVDD on the VDD pin must be sized according to the time needed by the converter to start up, when the device starts switching.
This time tSS depends on many parameters, among which transformer design, output capacitors, soft start feature and compensation network implemented on the COMP pin. Worst case is generally at full load.
Refer to the minimum specified value. Soft start feature can be implemented on the COMP pin through a simple capacitor which will be also used as the compensation network. In this case, the regulation loop bandwidth is rather low, because of the large value of this capacitor.
It mixes a high performance compensation network together with a separate high value soft start capacitor. Both soft start time and regulation loop bandwidth can be adjusted separately. Figure 17 shows a typical application of this function, with a latched shut down. VCOMP 1? More complex impedance can be connected on the COMP pin to achieve different compensation laws. A capacitor will provide an integrator function, thus eliminating the DC static error, and a resistance in series leads to a flat gain at higher frequency, insuring a correct phase margin.
This configuration is illustrated on figure As shown in figure 18 an additional noise filtering capacitor of 2. Figure 19 shows such a configuration. Note that R1 and C2 build the classical compensation network, and Q1 is injecting the slope compensation with the correct polarity from the oscillator sawtooth.
Figure 20 shows one possible schematic to be adapted depending the specific needs. If the proposed schematic is used, the pulse duration must be kept at a low value ns is sufficient for minimizing consumption. The optocoupler must be able to provide 20mA through the optotransistor. The minimum junction temperature at which over-temperature cut-out occurs is oC while the typical value is o C. They may be classified into two categories: - To minimise power loops: the way the switched power current must be carefully analysed and the corresponding paths must present the smallest inner loop area as possible.
This avoids radiated EMC noises, conducted EMC noises by magnetic coupling, and provides a better efficiency by eliminating parasitic inductances, especially on secondary side. To use different tracks for low level signals and power ones. In case of VIPer, these rules apply as shown on figure C6 must be as close as possible from T1. The signal components C2, ISO1, C3 and C4 are using a dedicated track to be connected directly to the source of the device.
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VIPER100A-E STMicroelectronics, VIPER100A-E Datasheet
SGS Thomson Microelectronics